Device and circuit design issues in SOI technology

Author

Shahidi, Ghavam G. ; Ajmera, Atul ; Assaderaghi, Fariborz ; Bolam, Ronald J. ; Hovel, Harold ; Leobandung, Effendi ; Rausch, Werner ; Sadana, Devendra ; Schepis, Dominic ; Wagner, Lawrence F. ; Wissel, Larry ; Wu, Kun ; Davari, Bijan

Author_Institution

Semicond. Res. & Dev. Center, IBM Corp., Hopewell Junction, NY, USA

fYear

1999

fDate

1999

Firstpage

339

Lastpage

346

Abstract

Partially-Depleted deep sub-micron CMOS on SOI technology is becoming a mainstream technology. This technology offers 20-35% performance gain over a bulk technology implemented with the same lithography. This paper first reviews the partially-depleted SOI device and describes reasons why it was chosen over fully depleted SOI device. Next the sources of performance gain on SOI are reviewed. SOI-unique circuit and technology issues that a designer must consider and account for are discussed next. Finally, a low-power application of SOI is reviewed

Keywords

CMOS integrated circuits; integrated circuit design; low-power electronics; silicon-on-insulator; SOI technology; circuit design; device design; low-power design; partially-depleted deep submicron CMOS IC; CMOS technology; Circuit synthesis; Delay effects; Equivalent circuits; Lithography; MOS devices; Performance gain; Research and development; System performance; Thickness control;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5443-5

Type

conf

DOI

10.1109/CICC.1999.777303

Filename

777303