A Novel Data-Parallel Coprocessor for Multimedia Signal Processing

Realizations of demanding embedded applications particularly in the field of signal processing often require high processing performance and low energy consumption which are far beyond what can be delivered by DSPs nowadays. A novel data-parallel coprocessor basing on the transport triggered architecture (TTA) is presented in this paper. The coprocessor consists of two powerful arithmetic clusters, the stream memory as well as the optimized data transport network, and is good at exploiting the data parallelism in the computation intensive multimedia applications. Also, the solution of the clock-gating in a gradual way is advanced for the low power dissipation. Then, a SoC chip involving the coprocessor is implemented using 0.18 mum CMOS process. Experimental results show that this coprocessor has good performance improvement for multimedia applications