Improving effective yield through error tolerant system design

This paper illustrates that the effective chip yield (memory) can be improved up to 10x by incorporating error tolerance in the system design rather than incorporating design for yield at the circuit stage. The proposed approach leverages the fact that some applications - by construction - are inherently error tolerant and therefore do not require a strict bound of 100% correctness to function. This concept is elaborated upon using a wireless communication system framework as a case study for application aware yield enhancement.