Performance evaluation of a Network on a Chip router using SystemC and TLM 2.0

Network on Chip (NoC) is a new paradigm to intercommunicate modules on the same dice that propose the replacement of traditional buses by routers and interface cards. The router is the main agent affecting performance and functionality of the overall system as it is in charge of delivering the information efficiently and reliably. A validation of the network is required before integrating it with other modules but due to its complexity, standard HDL design/simulation flow could be time and effort expensive for it. To overcome such difficulty, the SystemC high level approach can be used for rapid construction of virtual platforms that closely represent hardware behaviour and also for faster evaluation of multiple test scenarios. Through the use of the TLM 2.0 standard to speed up simulations, this work develops a router model and builds a 4×4 torus network. Routing algorithms, packet size and Virtual Channels are topics reviewed and studied here with the model constructed.