Title :
GaP source-drain SOI 1T-DRAM: Solving the key technological challenges
Author :
Pal, Arnab ; Nainani, Aneesh ; Zhiyuan Ye ; Xinyu Bao ; Sanchez, E. ; Saraswat, Krishna C.
Author_Institution :
Center of Integrated Syst., Stanford Univ., Sunnyvale, CA, USA
Abstract :
SOI based GaP source drain 1T DRAM with silicon channel is proposed. Using BJT-latch based programing, it is shown that the scalability of GaP-SD 1T-DRAM can be extended up to 20nm. Nickel alloying of GaP is proposed as a method to reduce the sheet and contact resistance of GaP source and drain. Using nickel alloying, the ON-current of the GaP-SD transistor is improved by an order and the proper scalability behavior is established.
Keywords :
DRAM chips; III-V semiconductors; bipolar transistors; contact resistance; flip-flops; gallium compounds; silicon-on-insulator; 1T-DRAM; BJT-latch based programing; GaP; GaP-SD transistor; SOI substrate; contact resistance; gallium phosphide source-drain; nickel alloying; scalability; sheet resistance; silicon channel; Alloying; Films; Logic gates; Nickel; Resistance; Silicon;
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013 IEEE
Conference_Location :
Monterey, CA
DOI :
10.1109/S3S.2013.6716573
