Design strategy to minimize rise time and silicon area of charge pump with only capacitive loads

An optimized strategy for designing charge pumps having only capacitive loads is presented. The design strategies developed are with minimum rise time and silicon are. The approach allows designers to define the number of stages that minimize silicon area (and minimize rise time) for a given input and output voltage. The approach was analytically developed and validated through simulations and experimental measurements on 0.18 mm EEPROM CMOS technology.