Title :
The challenge of designing global signals in UDSM CMOS
Author_Institution :
CMOS Solutions, Olga, WA, USA
Abstract :
This paper describes several of the challenges facing designers of global signals in high-performance, ultra-deep submicron (UDSM) CMOS designs. Practical guidelines and a building block approach are presented to solve or avoid problems with global signals as the technology shrinks to 0.25 micron and below. Power distribution is also treated as a global signal. Guidelines are presented for estimation, planning and implementation of global signals. The objective is to present a methodology that will provide a sound foundation for building systems-on-a-chip and resolve methodology and modeling issues early in the design cycle
Keywords :
CMOS integrated circuits; application specific integrated circuits; circuit CAD; integrated circuit design; buffers; building block approach; design challenges; design cycle; design tradeoffs; global signals design; guidelines; high-performance; implementation; inverters; modeling issues; planning; power distribution; systems-on-a-chip; ultra-deep submicron CMOS; Circuit simulation; Delay estimation; Guidelines; Inverters; Monitoring; Power distribution; Power system modeling; Signal design; Voltage; Wires;
Conference_Titel :
Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5443-5
DOI :
10.1109/CICC.1999.777317
