COFDM baseband processor on FPGA

This paper presents the design of a 12 Mb/s COFDM baseband processor compatible with the standard IEEE 802.11a. In this case, the architecture was described in VHDL, without use of IP cores or automatic generators, and the COFDM baseband processor with a cyclic prefix includes coarse and fine time synchronization system, and a channel coding system composed of a convolutional encoder with interleaver in the transmitter and a Viterbi decoder with deinterleaver in the receiver. Taking into account the experimental results, the COFDM processor presents a very good time-area trade-off, which is very suitable for SoC.