Substrate cross talk noise characterization and prevention in 0.35 μm CMOS technology

Author

Lee, John P Z ; Wang, Frank ; Phanse, Abhijit ; Smith, Linda C.

Author_Institution

Nat. Semicond. Corp., Santa Clara, CA, USA

fYear

1999

fDate

1999

Firstpage

479

Lastpage

482

Abstract

The results of substrate cross talk noise investigations using S-parameter measurement on device level are presented. Frequency domain analysis shows that the noise in a lightly doped p-type substrate is strongly dependent on layout geometry. Experimental approaches using guard ring (GR), isolation bar (IB), diffusion width (W), physical separation (S), and different DC bias condition are used to reduce the substrate noise. It is shown in this study that double GR structure with IB implementation can be very effective in shielding the substrate noise

Keywords

CMOS integrated circuits; S-parameters; crosstalk; electric noise measurement; frequency-domain analysis; integrated circuit layout; integrated circuit measurement; integrated circuit noise; isolation technology; mixed analogue-digital integrated circuits; 0.35 micron; DC bias condition; S-parameter measurement; diffusion width; double guard ring structure; frequency domain analysis; guard ring; isolation bar; layout geometry; lightly doped p-type substrate; noise shielding; physical separation; submicron CMOS technology; substrate crosstalk noise characterization; substrate crosstalk noise prevention; CMOS technology; Circuit noise; Circuit testing; Coupling circuits; Frequency domain analysis; MOSFETs; Noise measurement; Noise reduction; Semiconductor device noise; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5443-5

Type

conf

DOI

10.1109/CICC.1999.777326

Filename

777326