Title :
LB-packing-based floorplan design on DBL representation
Author :
Yan, Jin-Tai ; Lin, Kai-Ping ; Luo, Yue-Fong
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Chung Hua Univ., Hsinchu
Abstract :
In this paper, an LB-packing-based floorplan model is proposed to place a sequence of blocks on a dynamic stair contour. Furthermore, the representation of a double bound list(DBL) is proposed to model the geometrical adjacent relations in an LB-compact floorplan, and an LB-packing-based floorplan design based on DBL representation is proposed. The experimental results show that the LB-packing-based floorplan design on DBL representation obtains very promising results for MCNC benchmark circuits.
Keywords :
circuit layout CAD; integrated circuit layout; integrated circuit packaging; DBL representation; LB-compact floorplan; LB-packing-based floorplan design; double bound list; dynamic stair contour; Circuits; Compaction; Computer science; Cost function; Data structures; Design engineering; Solid modeling;
Conference_Titel :
Electronics, Circuits and Systems, 2005. ICECS 2005. 12th IEEE International Conference on
Conference_Location :
Gammarth
Print_ISBN :
978-9972-61-100-1
Electronic_ISBN :
978-9972-61-100-1
DOI :
10.1109/ICECS.2005.4633588
