DocumentCode
2952879
Title
A Strict-time Distributed Architecture for Digital Beamforming of Ultrasound Signals
Author
Camacho, Jorge ; Martínez, Oscar ; Parrilla, Montserrat ; Mateos, Raúl ; Fritsch, Carlos
Author_Institution
Inst. de Autom. Ind., Madrid
fYear
2007
fDate
3-5 Oct. 2007
Firstpage
1
Lastpage
6
Abstract
This work presents a strict timing-coherent digital signal processing architecture. The fundamental requirement is that programmable events can be produced within predictable time intervals with tight accuracies (timing errors <1 ns). There are several application fields where this characteristic is essential, as in ultrasound beamforming, where the system spreads over several processing modules. The followed approach defines a modular and scalable architecture (AMPLIA), configured as a multi-branch pipeline. This arrangement guarantees timing coherence along all the system, independently of the number of processing modules. The latency introduced by every module is automatically compensated and clock synchronization is achieved by Digital Clock Managers inside FPGAs. Furthermore, AMPLIA is a very simple to use architecture, involving a 32-bit data bus and only 8 control lines. An important element of the architecture is the Interface and Control Unit (ICU). This element couples the asynchronous communications with a host computer to the strictly timing- coherent domain of the system. Besides, it automatically performs the operations of parameter programming, triggering of acquisition-processing cycles, housekeeping functions and result retrieval, all within well defined time intervals. In the beamforming application, high timing resolution is achieved in emission by clock multiplication and by Lagrange interpolation in reception. This allows operating the overall system at the lower sampling clock frequency. Dynamic focusing is performed by Progressive Focusing Correction and processing rates of several Gsamples/s are achieved.
Keywords
acoustic signal processing; clocks; field programmable gate arrays; interpolation; pipeline processing; signal sampling; synchronisation; FPGA; Lagrange interpolation; acquisition-processing cycle triggering; clock multiplication; clock synchronization; digital beamforming; digital clock managers; digital signal processing architecture; dynamic focusing; interface-control unit; multibranch pipeline; parameter programming; progressive focusing correction; sampling clock frequency; strict-time distributed architecture; ultrasound signals; Accuracy; Array signal processing; Automatic control; Clocks; Communication system control; Computer architecture; Digital signal processing; Pipelines; Timing; Ultrasonic imaging; Beamforming; distributed architectures; timing resolution; ultrasound imaging;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent Signal Processing, 2007. WISP 2007. IEEE International Symposium on
Conference_Location
Alcala de Henares
Print_ISBN
978-1-4244-0829-0
Electronic_ISBN
978-1-4244-0830-6
Type
conf
DOI
10.1109/WISP.2007.4447598
Filename
4447598
Link To Document