A single-chip 1.6 billion 16-b MAC/s multiprocessor DSP

Author

Ackland, B. ; Anesko, A. ; Brinthaupt, D. ; Daubert, S.J. ; Kalavade, A. ; Knobloch, J. ; Micca, E. ; Moturi, M. ; Nicol, C.J. ; O´Neill, J.H. ; Othmer, J. ; Säckinger, E. ; Singh, K.J. ; Sweet, J. ; Terman, C.J. ; Williams, J.

Author_Institution

DSP & VLSI Syst. Res., AT&T Bell Labs., Holmdel, NJ, USA

fYear

1999

fDate

1999

Firstpage

537

Lastpage

540

Abstract

A MIMD multiprocessor DSP chip containing four 64-b processing elements (PEs) interconnected by a 128-b pipelined split transaction bus (STBus) is presented. Each PE contains a 32-b RISC core with DSP enhancements and a 64-b SIMD vector co-processor with four 16-b MACS and a vector reduction unit. PEs are connected to the STBus through re-configurable dual-ported snooping L1 cache memories that support shared memory multiprocessing using a modified-MESI data coherency protocol. High-bandwidth data transfers between system memory and on-chip caches are managed in a pipelined memory controller that supports multiple outstanding transactions. An embedded RTOS dynamically schedules multiple tasks onto the PEs. Process synchronization is achieved using cached semaphores. The 120 mm² 0.25 μm CMOS chip operates at 100 MHz and dissipates 4 W from a 3.3 V supply

Keywords

CMOS digital integrated circuits; digital signal processing chips; multiprocessing systems; parallel architectures; pipeline processing; 0.25 micron; 100 MHz; 16 bit; 3.3 V; 4 W; CMOS chip; Daytona architecture; MACS; RISC core; SIMD vector co-processor; dynamic scheduling; embedded RTOS; pipelined memory controller; reconfigurable L1 cache memory; semaphore; single-chip MIMD multiprocessor DSP; software development environment; split transaction bus; vector reduction unit; Cache memory; Control systems; Coprocessors; Digital signal processing; Digital signal processing chips; Dynamic scheduling; Memory management; Protocols; Reduced instruction set computing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5443-5

Type

conf

DOI

10.1109/CICC.1999.777338

Filename

777338