Title :
Wave pipelining YADDs-a feasibility study
Author :
Mukherjee, A. ; Marek-Sadowska, M. ; Long, S.I.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Abstract :
In this paper we study circuit structures obtained from direct mapping to pass transistor logic (PTL) of Yet Another Decision Diagrams (YADDs). These structures have almost equal delays along all the paths which makes wave pipelining possible. We discuss the details of a complete design, clocking and layout. In 0.5 μm CMOS technology, YADDs can be clocked at a fixed rate of 715 MHz for any function. Our experimental results suggest that 4 times increase of speed over standard cell design is on the average possible for the price of similar area increase
Keywords :
CMOS digital integrated circuits; VLSI; binary decision diagrams; circuit CAD; delays; high-speed integrated circuits; integrated circuit layout; logic CAD; pipeline processing; 0.5 micron; 715 MHz; CMOS technology; PTL; YADD structures; Yet Another Decision Diagrams; circuit structures; clocking; direct mapping; layout; pass transistor logic; wave pipelining; Binary decision diagrams; Boolean functions; CMOS technology; Clocks; Integrated circuit interconnections; Inverters; Logic circuits; Multiplexing; Pipeline processing; Propagation delay;
Conference_Titel :
Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5443-5
DOI :
10.1109/CICC.1999.777343
