Title :
Design impact of positive temperature dependence of drain current in sub 1 V CMOS VLSIs
Author :
Kanda, Kouichi ; Nose, Kouichi ; Kawaguchi, Hiroshi ; Sakurai, Takayasu
Author_Institution :
Inst. of Ind. Sci., Tokyo Univ., Japan
Abstract :
In sub 1 V CMOS designs, especially around 0.5 V CMOS designs, the on-state drain current of MOSFET´s shows positive temperature dependence, being different from the negative temperature dependence in the conventional voltage designs. Together with the low threshold voltage less than 0.2 V in the low-voltage CMOS, a possibility of temperature instability increases. The paper describes possible temperature instabilities in the low-voltage regime by using circuit simulation environments incorporating temperature change in time and experiments using MOSFET´s and 32-bit adder circuit in quarter micron CMOS technology with low threshold voltage of 0.25 V
Keywords :
CMOS digital integrated circuits; VLSI; circuit simulation; circuit stability; electric current; integrated circuit design; low-power electronics; thermal stability; 0.2 to 1 V; 0.25 micron; LV regime; MOSFET drain current; adder circuit; circuit simulation environments; low threshold voltage; low-voltage CMOS; onstate drain current; positive temperature dependence; sub 1 V CMOS VLSI designs; temperature instability; CMOS technology; Circuit simulation; Current measurement; Degradation; Delay; Integrated circuit measurements; MOS devices; Temperature dependence; Threshold voltage; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5443-5
DOI :
10.1109/CICC.1999.777344
