Circuit partitioning by quadratic Boolean programming for reconfigurable circuit boards

We propose a new quadratic Boolean programming problem formulation to partition a circuit for FPGA based reconfigurable circuit boards in which the routing topology among IC chips are predetermined. Nets passing through IC chips in their interconnections are considered in the formulation to complete their routing and to minimize the I/O pins used. We also describe a heuristic method to efficiently solve the problem. Experimental results show that our method generates the partitions in which the average reduction of the I/O pins used are up to 18% compared to the previous method for all the benchmark circuits tested