Low-power bit-serial Viterbi decoder for 3rd generation W-CDMA systems

Author

Suzuki, Hiroshi ; Chang, Yun-Nan ; Parhi, Keshab K.

Author_Institution

LSI Div., Kawasaki Steel Corp., Chiba, Japan

fYear

1999

fDate

1999

Firstpage

589

Lastpage

592

Abstract

This paper presents a low-power bit-serial Viterbi decoder chip with the coding rate r=1/3 and the constraint length K= 9 (256 states). This chip is targeted for high speed convolutional decoding for next generation wireless applications. The Add-Compare-Select (ACS) units have been designed using bit-serial arithmetic and a power efficient trace-back scheme and an application-specific memory have been developed for the trace-back operation. The chip was implemented using 0.5 μm CMOS technology and is operative at 20 Mbps under 3.3 V and at 2 Mbps under 1.8 V. The power dissipation is only 9.8 mW at 2 Mbps operation under 1.8 V

Keywords

CMOS digital integrated circuits; Viterbi decoding; application specific integrated circuits; code division multiple access; convolutional codes; digital arithmetic; digital radio; digital signal processing chips; high-speed integrated circuits; low-power electronics; mobile radio; wireless LAN; 0.5 micron; 1.8 to 3.3 V; 2 to 20 Mbit/s; 3rd generation W-CDMA systems; 9.8 mW; ACS unit design; CMOS decoder chip; add-compare-select units; application-specific memory; bit-serial Viterbi decoder; bit-serial arithmetic; high speed convolutional decoding; low-power Viterbi decoder; next generation wireless application; power efficient trace-back scheme; wideband CDMA systems; Arithmetic; CMOS technology; Convolutional codes; Decoding; Large scale integration; Magnetic memory; Multiaccess communication; Power dissipation; Steel; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5443-5

Type

conf

DOI

10.1109/CICC.1999.777350

Filename

777350