Title :
A low-power and low-noise CMOS prescaler for 900 MHz to 1.9 GHz wireless applications
Author :
Chang, W.-H. ; Pehlke, D.R. ; Yu, R.
Author_Institution :
Rockwell Sci. Center, Thousand Oaks, CA, USA
Abstract :
A high-speed dual-modulus prescaler has been developed in 0.36 μm CMOS. The prescaler was designed for low-power frequency synthesizers for 900 MHz to 1.9 GHz wireless applications. It provides programmable division ratio of 64, 65, 128, and 129. Power consumption was 2.9 mW with 1.9 GHz input frequency and 3.3 V power supply. The measured residual phase noises were -142 dBc/Hz at 100 Hz offset and -166 dBc/Hz at 100 kHz offset
Keywords :
CMOS logic circuits; direct digital synthesis; frequency synthesizers; high-speed integrated circuits; integrated circuit noise; low-power electronics; mobile radio; phase noise; prescalers; 0.36 micron; 2.9 mW; 3.3 V; 900 MHz to 1.9 GHz; dual-modulus prescaler; dynamic logic architecture; high-speed prescaler; low-noise CMOS prescaler; low-power CMOS prescaler; low-power frequency synthesizers; programmable division ratio; wireless applications; CMOS logic circuits; CMOS technology; Clocks; Delay; Flip-flops; Frequency conversion; Frequency synthesizers; Inverters; Modulation coding; Transceivers;
Conference_Titel :
Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5443-5
DOI :
10.1109/CICC.1999.777352
