Architectural Design of CA-Based Double Byte Error Correcting Codec

Author

Bhaumik, Jaydeb ; Janakiram, Balaji ; Chowdhury, Dipanwita Roy

Author_Institution

G.S. Sanyal Sch. of Telecommun., Indian Inst. of Technol., Kharagpur

fYear

2008

fDate

8-10 Dec. 2008

Firstpage

1

Lastpage

6

Abstract

Cellular Automata (CA) is a novel approach for designing byte error-correcting codes. The regular, modular and cascaded structure of CA can be economically built with VLSI technology. In this correspondence, a modular architecture of CA based (32, 28) byte error correcting encoder and decoder has been proposed. The design is capable of locating and correcting all double byte errors. CA-based implementation of the proposed decoding scheme provides a simple cost effective solution compared to the existing decoding scheme for the Reed-Solomon (RS) decoder, having double error correcting capability.

Keywords

VLSI; cellular automata; codecs; electronic engineering computing; error correction codes; logic design; VLSI technology; cellular automata; double byte error correcting codec; Application software; Codecs; Computer architecture; Computer errors; Decoding; Error correction; Error correction codes; Region 10; Sections; Very large scale integration; Byte Error Correcting Code; Cellular Automata; VLSI;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial and Information Systems, 2008. ICIIS 2008. IEEE Region 10 and the Third international Conference on

Conference_Location

Kharagpur

Print_ISBN

978-1-4244-2806-9

Electronic_ISBN

978-1-4244-2806-9

Type

conf

DOI

10.1109/ICIINFS.2008.4798442

Filename

4798442