Giga bit per second per pin differential CMOS circuits for pseudo ECL signaling

Author

Djahanshahi, Hormoz ; Hansen, Flemming ; Salama, C. André T

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

fYear

1999

fDate

1999

Firstpage

601

Lastpage

604

Abstract

This paper presents high-speed differential CMOS circuits for giga bit per second serial data transmission. The circuits include input and output (I/O) interfaces and a flipflop for retiming. Signal levels are compatible with industry standards for low-voltage positive ECL, with the possibility of ac-coupling to standard ECL systems. A differential open-drain circuit with pulsed bias and active pull-ups offers significantly improved speed performance for a transmitter and creates wide open eye patterns. The circuits were implemented in a 0.35 μm CMOS process and tested at 622 Mb/s and 1.24 Gb/s. The asynchronous performances of the transmitter and the receiver were tested at rates up to 2.5 Gb/s

Keywords

CMOS logic circuits; emitter-coupled logic; flip-flops; high-speed integrated circuits; low-power electronics; 0.35 micron; 1.24 Gbit/s; 2.5 Gbit/s; 622 Mbit/s; active pull-up; asynchronous receiver; asynchronous transmitter; flip-flop; high-speed differential CMOS circuit; input/output interface; low-voltage positive ECL; open eye pattern; open-drain circuit; pseudo-ECL signaling; pulsed bias; retiming; serial data transmission; CMOS technology; Circuit testing; Data communication; Detectors; Integrated circuit interconnections; Mirrors; Pulse circuits; Tail; Transmitters; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5443-5

Type

conf

DOI

10.1109/CICC.1999.777353

Filename

777353