DocumentCode :
2953598
Title :
Development and performance verification of the GANDALF high-resolution transient recorder system
Author :
Bartknecht, S. ; Fischer, H. ; Herrmann, F. ; Königsmann, K. ; Lauser, L. ; Schill, C. ; Schopferer, S. ; Wollny, H.
Author_Institution :
Dept. of Phys., Univ. of Freiburg, Freiburg, Germany
fYear :
2010
fDate :
24-28 May 2010
Firstpage :
1
Lastpage :
4
Abstract :
With present-day detectors in high energy physics one is often faced with short analog pulses of a few nanoseconds length which may cover large dynamic ranges. In many experiments both amplitude and timing information have to be measured with high accuracy. Additionally, the data rate per readout channel can reach several MHz, which makes high demands on the separation of pile-up pulses. For such applications we have built the GANDALF transient recorder with a resolution of 12bit@1GS/s and an analog bandwidth of 500 MHz. Signals are digitized and processed by fast algorithms to extract pulse arrival times and amplitudes in real-time and to generate experiment trigger signals. With up to 16 analog channels, deep memories and a high data rate interface, this 6U-VME64x/VXS module is not only a dead-time free digitization unit but also has huge numerical capabilities provided by the implementation of a Virtex5-SXT FPGA. Fast algorithms implemented in the FPGA may be used to disentangle possible pile-up pulses and determine timing information from sampled pulse shapes with a time resolution in the picosecond range. Recently the application spectrum has been extended by designing a digital input mezzanine card with 64 differential inputs. This allows for the implementation of TDCs, scalers, mean-timers and logic functions in the GANDALF module.
Keywords :
analogue-digital conversion; field programmable gate arrays; nuclear electronics; readout electronics; real-time systems; 6U-VME64x-VXS module; GANDALF development; GANDALF high-resolution transient recorder system; GANDALF module; GANDALF performance verification; Virtex5-SXT FPGA; amplitude information; analog bandwidth; analog channels; bandwidth 500 MHz; data rate interface; dead-time free digitization unit; differential inputs; digital input mezzanine card; experiment trigger signals; high energy physics; large dynamic ranges; pile-up pulses; pulse arrival amplitudes; pulse arrival times; readout channel; short analog pulses; timing information; Clocks; Compass; Detectors; Field programmable gate arrays; Signal resolution; Timing; Transient analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Real Time Conference (RT), 2010 17th IEEE-NPSS
Conference_Location :
Lisbon
Print_ISBN :
978-1-4244-7108-9
Type :
conf
DOI :
10.1109/RTC.2010.5750360
Filename :
5750360
Link To Document :
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