DocumentCode
2953679
Title
Design and implementation of high speed code extractor
Author
Guican, Chen ; Jun, Cheng ; Xiaoyan, Tang
Author_Institution
Dept. of Microelectron. Eng., Xi´´an Jiaotong Univ., China
fYear
1996
fDate
21-24 Oct 1996
Firstpage
218
Lastpage
220
Abstract
By taking an example of using Xilinx FPGA device to implement the high speed code extractor we introduce a way to meet the time constraints of the demands of the high speed circuit in the phase of the schematic design. We employ global buffers using flip-flop location and using TIMESPEC component in the schematic design to implement a design that operates at high frequency (52 MHz) successfully and easily
Keywords
buffer circuits; field programmable gate arrays; flip-flops; 52 MHz; TIMESPEC component; Xilinx FPGA device; flip-flop location; global buffers; high speed circuit; high speed code extractor; time constraints; Clocks; Communication system software; Delay effects; Field programmable gate arrays; Flexible printed circuits; Flip-flops; Frequency conversion; Liquid crystal displays; Routing; Signal design;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 1996., 2nd International Conference on
Conference_Location
Shanghai
Print_ISBN
7-5439-0940-5
Type
conf
DOI
10.1109/ICASIC.1996.562791
Filename
562791
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