Title :
A new technique for standby leakage reduction in high-performance circuits
Author :
Ye, Y. ; Borkar, S. ; De, V.
Author_Institution :
Microcomputer. Res. Labs., Intel Corp., Hillsboro, OR, USA
Abstract :
A new standby leakage control technique, which exploits the leakage reduction offered by transistor stacks with "more than one \´off\´ device", demonstrates 2/spl times/ reduction in standby leakage power for a 32-bit static CMOS adder in a low-Vt, sub-1V, 0.1 /spl mu/m technology. Leakage reduction is achieved with minimal overheads in area, power and process technology. The dynamics of leakage reduction due to transistor stacks, and its influence on the overall leakage power of large circuits are elucidated for the first time.
Keywords :
CMOS logic circuits; adders; circuit simulation; leakage currents; logic simulation; 0.1 micron; 32 bit; high-performance circuits; overall leakage power; process technology; standby leakage reduction; static CMOS adder; transistor stacks; Adders; CMOS logic circuits; CMOS technology; Capacitance; Leakage current; Logic devices; Logic gates; MOS devices; Subthreshold current; Voltage;
Conference_Titel :
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4766-8
DOI :
10.1109/VLSIC.1998.687996
