Title :
A novel powering-down scheme for low Vt CMOS circuits
Author :
Kumagai, K. ; Iwaki, H. ; Yoshida, H. ; Suzuki, H. ; Yamada, T. ; Kurosawa, S.
Author_Institution :
ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan
Abstract :
In this paper, a novel powering-down scheme with a virtual power/ground rails clamp (VRC) circuit is proposed. It features the 98% off-leakage current reduction, without the operating speed degradation and the high Vt transistors. The VRC scheme does not need the extra circuits and the timing design for data holding in the sleep mode. This effectiveness has been confirmed by the 24-bit multiplier-accumulator, using 0.25 /spl mu/m CMOS double-layer metal technology.
Keywords :
CMOS logic circuits; integrated circuit design; integrated circuit measurement; leakage currents; low-power electronics; multiplying circuits; 0.25 micron; 24 bit; CMOS double-layer metal technology; data holding; low Vt CMOS circuits; multiplier-accumulator; off-leakage current reduction; powering-down scheme; sleep mode; virtual power/ground rails clamp circuit; CMOS technology; Circuit simulation; Clamps; Degradation; Diodes; Leakage current; Rails; Signal design; Timing; Voltage;
Conference_Titel :
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4766-8
DOI :
10.1109/VLSIC.1998.687998
