DocumentCode
2954344
Title
The Intel® Many Integrated Core Architecture
Author
Duran, Alejandro ; Klemm, Michael
fYear
2012
fDate
2-6 July 2012
Firstpage
365
Lastpage
366
Abstract
In recent years, an observable trend in High Performance Computing (HPC) architectures has been the inclusion of accelerators, such as GPUs and field programmable arrays (FPGAs), to improve the performance of scientific applications. To rise to this challenge Intel announced the Intel® Many Integrated Core Architecture (Intel® MIC Architecture). In contrast with other accelerated platforms, the Intel MIC Architecture is a general purpose, manycore coprocessor that improves the programmability of such devices by supporting the well-known shared-memory execution model that is the base of most nodes in HPC machines. In this presentation, we will introduce key properties of the Intel MIC Architecture and we will also cover programming models for parallelization and vectorization of applications targeting this architecture.
Keywords
field programmable gate arrays; graphics processing units; parallel architectures; shared memory systems; GPU; Intel MIC architecture; Intel many integrated core architecture; accelerators; field programmable arrays; high performance computing; many core coprocessor; parallelization; programming model; shared-memory execution model; vectorization; Computer architecture; Coprocessors; Hardware; Microwave integrated circuits; Program processors; Programming; Syntactics;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computing and Simulation (HPCS), 2012 International Conference on
Conference_Location
Madrid
Print_ISBN
978-1-4673-2359-8
Type
conf
DOI
10.1109/HPCSim.2012.6266938
Filename
6266938
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