DocumentCode
2954579
Title
The design of high-speed sigma-delta modulator
Author
Hong, Li ; Hao, Min ; Lee, C.J.
Author_Institution
ASIC & Syst. Key State Lab., Fudan Univ., Shanghai, China
fYear
1996
fDate
21-24 Oct 1996
Firstpage
248
Lastpage
251
Abstract
The design for high speed ΣΔ modulator is discussed, Comparison between current-mode and switched-capacitor ΣΔ modulator performance is given. Fast-speed CMOS amplifier and comparator are designed to implement the circuit. In 1.08 μm CMOS process current-mode ΣΔ modulator achieves 100 MHz sampling rate
Keywords
CMOS integrated circuits; comparators (circuits); current-mode logic; sigma-delta modulation; switched capacitor networks; 1.08 micron; 100 MHz; CMOS amplifier; CMOS comparator; current-mode ΣΔ modulator; high-speed sigma-delta modulator; sampling rate; switched-capacitor ΣΔ modulator; CMOS technology; Capacitors; Circuits; Clocks; Delta-sigma modulation; Frequency; Signal sampling; Switches; Transconductors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 1996., 2nd International Conference on
Conference_Location
Shanghai
Print_ISBN
7-5439-0940-5
Type
conf
DOI
10.1109/ICASIC.1996.562799
Filename
562799
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