Hardware implementation of shortened (48,38) Reed Solomon forward error correcting code

Author

Khan, M.A. ; Afzal, S. ; Manzoor, R.

Author_Institution

Dept. of VLSI Design & Implementation, Adv. Eng. Res. Organ., Rawalpindi

fYear

2003

fDate

9-9 Dec. 2003

Firstpage

90

Lastpage

95

Abstract

Transmitting information with accuracy is vital in any communication system. For this reason, forward error correction schemes are widely used to lower the error probability and hence increase the transmission accuracy. Reed Solomon is one of the most widely used forward error correcting block codes, and is capable of detecting and correcting multiple errors, particularly focusing on burst errors. This paper presents a shortened (48,38) Reed Solomon (RS) forward error-correcting code from a hardware implementation point of view. Detailed mathematical equations explaining the algorithm are also included in the paper. MATLAB, fixed point C and Verilog implementations of the algorithm have also been tested and verified, for a noisy channel as well

Keywords

Galois fields; Reed-Solomon codes; block codes; cyclic codes; error correction codes; forward error correction; FEC methods; Galois fields; RS code hardware implementation; Reed Solomon forward error correcting code; burst errors; cyclic linear block codes; error probability reduction; multiple error correction; noisy channels; shortened RS code; Block codes; Codecs; Equations; Error correction codes; Field programmable gate arrays; Forward error correction; Hard disks; Hardware; Reed-Solomon codes; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Multi Topic Conference, 2003. INMIC 2003. 7th International

Conference_Location

Islamabad

Print_ISBN

0-7803-8183-1

Type

conf

DOI

10.1109/INMIC.2003.1416621

Filename

1416621