DocumentCode :
2954646
Title :
5 GByte/s data transfer scheme with bit-to-bit skew control for synchronous DRAM
Author :
Sato, T. ; Nishio, Y. ; Sugano, T. ; Nakagome, Y.
Author_Institution :
Semicond. & Integrated Circuits Div., Hitachi Ltd., Tokyo, Japan
fYear :
1998
fDate :
11-13 June 1998
Firstpage :
64
Lastpage :
65
Abstract :
With the rapid increase of MPU´s operating frequency, faster data transfer is required for memory systems. When the data bus frequency exceeds 100 MHz, controlling flight time variation becomes more crucial. This paper describes a 5 GByte/s data transfer scheme (313 MHz; /spl times/64 bit, double data rate) suitable for synchronous DRAM memory systems. A new multi-output controlled delay circuit of 30 ps resolution eliminates incongruent skew between data traces, and required improvements in the electrical characteristics are illustrated.
Keywords :
DRAM chips; compensation; delay circuits; 313 MHz; 5 GByte/s; 64 bit; bit-to-bit skew control; data bus frequency; data transfer scheme; flight time variation; memory systems; multi-output controlled delay circuit; synchronous DRAM; Capacitance; Circuits; Clocks; Connectors; Control systems; Delay; Frequency conversion; Jitter; Packaging; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4766-8
Type :
conf
DOI :
10.1109/VLSIC.1998.688005
Filename :
688005
Link To Document :
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