Low-power robust beat detection in ambulatory cardiac monitoring

With new advances in ambulatory monitoring new challenges appear due to degradation in signal quality and limitations in hardware requirements. Existing signal analysis methods should be re-evaluated in order to adapt to the restrictive requirements of these new applications. With this motivation, we chose a robust beat detection algorithm and optimized it further to be running in an embedded platform within a cardiac monitoring sensor node. The algorithm was designed in floating point in Matlab and evaluated in order to study its performance under a wide range of conditions. The initial PC version of the algorithm obtained a good performance under a wide variety of conditions (Se = 99.65% and + P = 99.79% on the MIT/BIH arrhythmia database and Se = 99.88%, + P = 99.93% on our own database with ambulatory data). In this study, the algorithm is adapted and further optimized to work in real time on an embedded digital processor, while keeping this performance without degradation. The run-time memory usage of the application was of 150 KB with an execution time of 1.5 million cycles and an average power consumption of 494 ¿W for an ECG of 3 seconds length and sampling frequency of 198 Hz. The algorithm implementation in a general purpose processor will put significant limits on the performance in terms of power consumption. We propose possible specifications for an application-optimized processor for more efficient ECG analysis.