Fast parallel architecture for syndrome convolutional decoder

This paper presents a parallel architecture for the syndrome convolutional decoder. It is build-up of a parallel convolutional encoder and a syndrome correction block. The proposed architecture combines combinatorial and pipeline parallelism techniques. Using both techniques allows to limit the critical path increase on higher levels of parallelism, i.e. limit the operating frequency decrease. Data rates up to 4.78 Gbits/s have been obtained for a 1/2 -rate code implementation on a FPGA device of the ALTERA Flex10KE family.