Effect of number of faults on NoC power and performance

According to international technology roadmap for semiconductors (ITRS), before the end of this decade, we will be entering the era of a billion transistors on a single chip. The major threat toward the achievement of billion transistor on a chip is poor scalability of current interconnect infrastructure. With the advent of "network on chip (NoC)" various characters and methodologies of traditional networks were hardly considered on-chip. Failure, power and area are the major concepts that should be considered when migrating from traditional interconnection networks to NoCs. In this paper we study the effects of faulty links and nodes on power and performance of mesh based NoC, Also several routing algorithms have been implemented and simulated using a cycle accurate VHDL model of NoC.