Thermal-aware task allocation, memory mapping, and task scheduling for 3D stacked memory and processor architecture

Heterogeneous integration enabled by 3D technology is one of the innovations for future microprocessor design. By the heterogeneous integration of memory and multi-core processor in the 3D architecture, DRAM stacking offer much higher memory bandwidth for instruction and data accesses, and mitigating the memory wall problem in off-chip DRAM design. However, this stacking architecture will come out a serious thermal problem. In this paper, we propose a thermal-aware task allocation, memory mapping, and task scheduling methodology for the stacked memory and multi-core processor architecture. By considering the thermal effect in both the processor cores and the memory tiers, experimental results from the thermal simulation tool show that our approach can reduce the heat dissipation effectively.