Field-programmable gate array implementation of low-density parity-check codes decoder and hardware testbed

The prototyping design of the channel coding in communication systems such as IEEE 802.16e (WiMAX) has become more sophisticated because of the increasing need for interoperability. Understanding its performance in the design and implementation of forward error correction codes in a real-time manner is necessary for rapid prototyping in research areas that are primarily based on emulation and stand-alone tests. This paper presents the design, implementation, experimental verification, and validation of the proposed LDPC decoder using a real-time FPGA based baseband test. The design of the LDPC decoder is described. In addition, a description of the hardware components that covers the important parts of the system from RF to channel decoding is included. The overall architecture of the baseband digital signal processing is simply illustrated, and details of the data acquisition module are provided. On the implementation and testing results, the throughput and latency at all the code rates specified in IEEE 802.16e are shown. Furthermore, the results for the architectural complexity and performance in terms of the bit error rates over the testbed show that the proposed flexible design for IEEE 802.16e exhibits potential under a practical environment.