Minimizing the number of phases in clocked digital designs derived using modulo scheduling techniques

We address a problem that arises in minimizing the clock period for synchronous digital designs using modulo scheduling for software pipelining. Once the minimal clock period is determined, the problem is how to simultaneously: (1) compute a valid periodic schedule of the computational elements, (2) place registers, and (3) minimize the number of phases. A minimal number of phases allow to reduce the complexity of the clock generation and distribution tasks. In this paper, we propose a mathematical formulation to this problem, and a mixed integer linear program to solve it. We also present how the solution space of this mixed integer linear program can be pruned. We experimentally show the effectiveness of the proposed approach using known benchmark circuits.