New efficient design of digital comparator

Author

Guangjie, Wang ; Shimin, Sheng ; Lijiu, Ji

Author_Institution

Inst. of Microelectron., Beijing Univ., China

fYear

1996

fDate

21-24 Oct 1996

Firstpage

263

Lastpage

266

Abstract

The digital comparator is a widely used circuit block. The typical versions using static CMOS logic have been well known. In this paper we present a new efficient design-MCP, which employs Manchester chain to fulfil the compare operation. Compared with the static implementations, MCP´s highest operating frequency (125 MHz) is much higher. At the same operating frequency, MCP´s power dissipation is 15%-22% lower than static version´s. The layout area of MCP is only 87.6% of the static´s and it is very convenient for implementing parallel or pipeline structure that is important for high performance VLSI design. By a series of optimizations the MCP gained a good noise immunity, though it is sensitive to noise glitches for its dynamic structure. MCP is a high quality function block and suitable for high performance VLSI design

Keywords

CMOS logic circuits; VLSI; comparators (circuits); integrated circuit design; integrated circuit noise; logic design; 125 MHz; CMOS dynamic logic; MCP; digital comparator design; dynamic structure; high performance VLSI design; noise immunity; parallel structure; pipeline structure; CMOS logic circuits; Circuit noise; Clocks; Crosstalk; Equations; Frequency; Logic functions; Microelectronics; Power dissipation; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 1996., 2nd International Conference on

Conference_Location

Shanghai

Print_ISBN

7-5439-0940-5

Type

conf

DOI

10.1109/ICASIC.1996.562803

Filename

562803