Design of digital circuits/systems with built-in testability

An algorithm has been proposed for incorporating built-in testability in the design of two-level AND-OR networks. The prime objective of testable design is achieved by adding some control inputs and gates (controllability) or to add some outputs (observability) in a given realization, so that the final circuit can be easily tested by using only a single spectral coefficient, namely, r₀. This procedure eliminates the need of test vector generation and expensive fault simulation. There is no storage problem which is associated with classical test procedure because it requires the knowledge of only one characteristics of the fault-tree circuit, namely, r₀ spectral coefficient.