Capacitor placement using genetic algorithms to reduce switching noise

This work investigates the capacitor placement on a printed circuit board (PCB) to reduce the effect of simultaneous switching noise (SSN) as a genetic algorithm (GA) search problem. The objective is to determine the minimum number of added capacitors, and hence cost, and their position on the PCB, while keeping the maximum voltage deviation within some specified noise margin. The presence of capacitors at the selected positions is represented by a stream of zeros and ones, which is interpreted as a genotype and manipulated using GA operators to systematically approach an optimal solution. At each step or generation of the GA the fitness of genotypes are assessed using linear transient circuit analyses by determining maximum voltage dip and number of capacitors needed. The circuit analysis is made efficient by formulating the problem in such a way that the transient analysis of each genotype involves a single formation and inversion of the nodal admittance matrix done at the onset of the process.