• DocumentCode
    2956070
  • Title

    Dual-Layer Cooperative Error Control for Reliable Nanoscale Networks-on-Chip

  • Author

    Yu, Qiaoyan ; Ampadu, Paul

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Rochester, Rochester, NY, USA
  • fYear
    2009
  • fDate
    7-9 Oct. 2009
  • Firstpage
    431
  • Lastpage
    439
  • Abstract
    We propose a framework that allows dual-layer cooperative error control in a nanoscale network-on-chip (NoC), to simultaneously improve reliability, performance and energy efficiency. The framework combines a configurable routing algorithm in the network layer and an adaptive error control coding scheme in the datalink layer. When the network layer detects an increase in network congestion, either the routing algorithm is switched from deterministic to partially adaptive routing or the error controls schemes is adjusted to a powerful mode. In high noise conditions, the adaptive error control in the datalink layer is switched to a more powerful error control mode, cooperating with the configurable routing algorithm. The resulting dual-layer framework allows reliability and network congestion to be managed dynamically. Simulation results show that the proposed method improves the average latency up to 24% and the average energy up to 27% compared to the single layer error control, with 8% area overhead.
  • Keywords
    VLSI; integrated circuit noise; integrated circuit reliability; network-on-chip; VLSI; adaptive error control; adaptive error control coding scheme; average energy; average latency; configurable routing algorithm; datalink layer; dual-layer cooperative error control; energy efficiency; nanoscale networks-on-chip reliability; network congestion; noise conditions; routing algorithm; Adaptive control; Computer network reliability; Crosstalk; Error correction; Fault tolerant systems; Network-on-a-chip; Programmable control; Routing; System-on-a-chip; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 2009. DFT '09. 24th IEEE International Symposium on
  • Conference_Location
    Chicago, IL
  • ISSN
    1550-5774
  • Print_ISBN
    978-0-7695-3839-6
  • Type

    conf

  • DOI
    10.1109/DFT.2009.48
  • Filename
    5372226