DocumentCode
2956129
Title
Self-timed Booth´s multiplier
Author
Pang, Tin-Chak-Johnson ; Choy, Chiu-Sing ; Chan, Cheong-Fat ; Cham, Wai-Kuen
Author_Institution
Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, Hong Kong
fYear
1996
fDate
21-24 Oct 1996
Firstpage
280
Lastpage
283
Abstract
This paper presents some methods to improve the performance of an asynchronous system. Firstly, the structure of micropipeline, 2-phase and 4-phase handshake control protocol, asymmetrical delay element and delay selection circuit are discussed. Then we demonstrate how to use these circuit techniques to design the self-timed 8×8 Booth´s multiplier. The performance of the circuit using these improvement techniques and different handshake control protocols are discussed and compared
Keywords
asynchronous circuits; delay circuits; logic design; multiplying circuits; pipeline arithmetic; protocols; timing; asymmetrical delay element; asynchronous system; delay selection circuit; handshake control protocol; micropipeline; self-timed Booth multiplier; Circuit simulation; Clocks; Control systems; Delay effects; Delay estimation; Digital systems; Energy consumption; Logic; Protocols; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 1996., 2nd International Conference on
Conference_Location
Shanghai
Print_ISBN
7-5439-0940-5
Type
conf
DOI
10.1109/ICASIC.1996.562807
Filename
562807
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