Thermal Driven Test Access Routing in Hyper-interconnected Three-Dimensional System-on-Chip

The rapid emergence of three dimensional integration using a ``Through-Silicon-Via´´ (TSV) process calls for research activities on testing and design for testability. Compared to the traditional 2D designs, the 3D-SoC poses great challenges in testing, such as three dimensional placement of cores and test resources, severe chip overheating due to the nonuniform distribution of power density in 3D, and 3D test access routing. In this work, we propose an effective and efficient test access routing and resource partitioning scheme to tackle the 3D-SoC test challenges. We develop a simple and scalable 3D-SoC test thermal model for thermal compatibility analysis. We construct a 3-D test access architecture for efficient test access routing, and partition the limited test resources to facilitate a thermal-aware test schedule while minimizing the overall test time. The promising results are demonstrated by extensive simulation on ITC´02 benchmark SoCs.