Title :
A 5.3 GB/s 32 Mb embedded SDRAM core with slightly boosting scheme
Author :
Yamazaki, A. ; Yamagata, T. ; Hatakenaka, M. ; Miyanishi, Astushi ; Hayashi, I. ; Tomishima, S. ; Mangyo, A. ; Yukinari, Y. ; Tatsumi, T. ; Matsumura, M. ; Arimoto, K. ; Yamada, M.
Author_Institution :
ULSI Lab., Mitsubishi Electr. Corp., Itami, Japan
Abstract :
A slightly boosting (SB) scheme has been proposed for improving transistor performance in system LSIs. Using this scheme, a 32 Mb embedded SDRAM core, which operates at a 166 MHz clock frequency, has been developed. The access time of the SDRAM core has also been improved, and 4 cycles of the RAS latency at 166 MHz has been achieved. The multi-select block write (MSBW) scheme is suited to the embedded SDRAM core having a wide data bus, and it improves the performance in graphic applications. The synchronous direct memory access test (SDMAT) circuit makes it easy to evaluate the embedded SDRAM core, and it realizes the 256 b multi-bit test.
Keywords :
CMOS memory circuits; DRAM chips; VLSI; storage management; 0.3 micron; 166 MHz; 3.3 V; 32 Mbit; 5.3 GB/s; CMOS synchronous DRAM; RAS latency; access time; dynamic RAM; embedded SDRAM core; graphics applications; multi-select block write scheme; slightly boosting scheme; synchronous direct memory access test circuit; system LSIs; Boosting; Circuit testing; Clocks; Frequency; Large scale integration; Logic arrays; Logic circuits; Random access memory; SDRAM; Voltage;
Conference_Titel :
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4766-8
DOI :
10.1109/VLSIC.1998.688015
