• DocumentCode
    2956215
  • Title

    Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone Partitioning

  • Author

    Neophytou, Stelios ; Michael, Maria K. ; Christou, Kyriakos

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Cyprus, Nicosia, Cyprus
  • fYear
    2009
  • fDate
    7-9 Oct. 2009
  • Firstpage
    401
  • Lastpage
    409
  • Abstract
    Testing modeled faults multiple times has been shown to increase the likelihood of a test set to detect non-modeled faults, either static or dynamic, when compared to a single detect test set. Test sets that guarantee detecting every modeled fault with at least n different tests are known as n-detect test sets. Moreover, recent investigations examine how different the various tests for a fault should be, in order to further increase their ability in detecting defects. This work proposes a new test generation methodology for multiple-detect (including n-detect) test sets that increases their diversity in terms of the various fault propagation paths excited by the different tests. Specifically, the various tests per modeled fault are guaranteed to propagate the fault effect via different propagation paths. The proposed method can be applied to any linear, to the circuit size, static or dynamic fault model for multiple fault detections, such as the stuck-at or transition delay fault models, and avoids any path or path segment enumeration. Experimental results show increased numbers of propagation paths and non-modeled fault coverages when compared to traditional n-detect test sets.
  • Keywords
    VLSI; fault location; testing; VLSI microchips; circuit size; diverse test sets; fault cone partitioning; fault detections; fault propagation paths; non-modeled faults; path segment enumeration; test generation methodology; transition delay fault models; Circuit faults; Circuit testing; Delay; Electrical fault detection; Fault detection; Fault tolerant systems; Intelligent networks; Intelligent systems; System testing; Very large scale integration; ATPG; multiple-detect test sets; n-detect test sets; propagation paths;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 2009. DFT '09. 24th IEEE International Symposium on
  • Conference_Location
    Chicago, IL
  • ISSN
    1550-5774
  • Print_ISBN
    978-0-7695-3839-6
  • Type

    conf

  • DOI
    10.1109/DFT.2009.24
  • Filename
    5372233