Title :
The design of an ASIC-multiplexer used in digital communication
Author :
Han Xingcheng ; Shao Zhibiao
Author_Institution :
Xi´an Jiaotong Univ.
Abstract :
This paper presents a novel design of communication ASIC multiplexer, which is an asynchronous system with positive code speed justification and consists of about eighty thousand integrated MOSFETs. In the multiplexer, the clocking block and digital locked-loops were designed. The designed system can be used in two different modes: the system allows 2/8 Mb multiplexing function of 8/34 Mb multiplexing function. This design was simulated and verified by EDA tool CADENCE Software, and the multiplexing function had been accomplished by FPGA
Keywords :
application specific integrated circuits; asynchronous circuits; circuit CAD; digital communication; field programmable gate arrays; logic CAD; multiplexing equipment; time division multiplexing; timing; 2 to 34 Mbit/s; ASIC multiplexer; CADENCE software; EDA tool; FPGA; MOS IC; asynchronous system; clocking block; digital communication; digital locked-loops; positive code speed justification; Application specific integrated circuits; Clocks; Demultiplexing; Digital communication; Electronic design automation and methodology; Field programmable gate arrays; Frequency synchronization; MOSFETs; Software tools; Time division multiplexing;
Conference_Titel :
ASIC, 1996., 2nd International Conference on
Conference_Location :
Shanghai
Print_ISBN :
7-5439-0940-5
DOI :
10.1109/ICASIC.1996.562808
