DocumentCode :
2956428
Title :
An Architecture Design of Threshold-Based Best-Basis Algorithm
Author :
Aroutchelvame, S.M. ; Raahemifar, K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, Ont.
fYear :
2006
fDate :
9-12 July 2006
Firstpage :
1273
Lastpage :
1276
Abstract :
The best-basis algorithm has gained much importance on textured-based image compression and denoising of signals. In this paper, an architecture for the wavelet-packet based best-basis algorithm for images is proposed. The paper also describes the architecture for best-tree selection from 2D wavelet packet decomposition. The precision analysis of the proposed architecture is also discussed and the result shows that increase in the precision of input pixel greatly increases the signal-to-noise ratio (SNR) per pixel whereas increase in the precision of filter coefficient does not greatly help in improving the SNR value. The proposed architecture is described in VHDL at the RTL level, simulated successfully for its functional correctness and implemented in an FPGA
Keywords :
data compression; field programmable gate arrays; filtering theory; hardware description languages; image coding; image denoising; image texture; 2D wavelet packet decomposition; FPGA; RTL level; VHDL; field programmable gate array; filter precision; hardware description language; image denoising; textured-based image compression; threshold-based best-basis algorithm; Algorithm design and analysis; Computer architecture; Cost function; Hardware; Image coding; Noise reduction; Signal design; Transform coding; Wavelet packets; Wavelet transforms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multimedia and Expo, 2006 IEEE International Conference on
Conference_Location :
Toronto, Ont.
Print_ISBN :
1-4244-0366-7
Electronic_ISBN :
1-4244-0367-7
Type :
conf
DOI :
10.1109/ICME.2006.262770
Filename :
4036839
Link To Document :
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