A novel floorplan representation with random contour corner selecting scheme

Floorplanning has played a crucial role in the VLSI physical design process, while a lot of focus has been put on the representation methodologies for the floorplan optimization in the recent researches. In this work, we propose an efficient P-admissible representation, called random contour corner (RCC), for non-slicing floorplans. It depends on a two-section random code, representing the sequence and location of the blocks respectively. The objective is to improve both area and wire length. For the optimization procedure, we apply a simulated annealing (SA) algorithm. The method is quite simple and time efficient for implementation even on large-scale integration floorplans, and the run time complexity for the algorithm is O(nlogn). The experimental results show that our proposed method achieves promising results by comparing with some other representations (O-tree, B*-tree and TCG) on basic MCNC benchmark circuits.