DocumentCode :
2956498
Title :
Minimizing Observation Points for Fault Location
Author :
Udar, Snehal ; Kagaris, Dimitri
Author_Institution :
Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
fYear :
2009
fDate :
7-9 Oct. 2009
Firstpage :
263
Lastpage :
267
Abstract :
We investigate the benefit of inserting observation points in a circuit in order to improve its diagnostic resolution. The insertion of the points is done so that each fault has a unique signature on these points under at least one of the applied test patterns. The observation points are scan-like elements that serve as test-phase outputs and can be organized in and observed through one or multiple chains. Experimental results show good tradeoffs between number of observation points that need to be inserted and diagnostic resolution achieved.
Keywords :
VLSI; fault location; integrated circuit testing; VLSI; diagnostic resolution; fault location; observation points; scan-like elements; test patterns; test-phase outputs; Automatic test pattern generation; Circuit faults; Circuit testing; Dictionaries; Fault detection; Fault diagnosis; Fault location; Fault tolerant systems; Hardware; Test pattern generators; Fault diagnosis; Fault location; Test point insertion;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2009. DFT '09. 24th IEEE International Symposium on
Conference_Location :
Chicago, IL
ISSN :
1550-5774
Print_ISBN :
978-0-7695-3839-6
Type :
conf
DOI :
10.1109/DFT.2009.56
Filename :
5372249
Link To Document :
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