• DocumentCode
    2956552
  • Title

    Can Functional Test Achieve Low-cost Full Coverage of NoC Faults?

  • Author

    Lubaszewski, Marcelo

  • Author_Institution
    Electr. Eng. Dept., UFRGS - Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
  • fYear
    2009
  • fDate
    7-9 Oct. 2009
  • Firstpage
    224
  • Lastpage
    224
  • Abstract
    Abstract form only given. This talk focuses on the functional testing of the NoC infrastructure. Herein, we are seeking for the integration of the test of interconnects and routers, at the lowest possible cost. Therefore, a manufacturing test strategy is proposed, that considers more realistic, logic level fault models, and attempts to fully cover faults that affect both the router logic and the communication channel wires. A functional-based approach is preferred, to reduce NoC re-design costs and to provide at-speed testing. However, scan and BISTbased approaches may be required to enhance both fault coverage and test application time.
  • Keywords
    built-in self test; integrated circuit interconnections; integrated circuit testing; network-on-chip; at-speed testing; built-in self test; communication channel wires; fault coverage; functional testing; integrated circuit interconnections; logic level fault models; manufacturing test strategy; network-on-chip; router logic; test application time; Fault detection; Fault tolerant systems; Logic testing; Multicore processing; Multiplexing; Network-on-a-chip; System testing; System-on-a-chip; Telecommunication network reliability; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 2009. DFT '09. 24th IEEE International Symposium on
  • Conference_Location
    Chicago, IL
  • ISSN
    1550-5774
  • Print_ISBN
    978-0-7695-3839-6
  • Type

    conf

  • DOI
    10.1109/DFT.2009.62
  • Filename
    5372252