DocumentCode
2956709
Title
Analysis of Resistive Open Defects in a Synchronizer
Author
Kim, Hyoung-Kook ; Jone, Wen-Ben ; Wang, Laung-Terng
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Cincinnati, Cincinnati, OH, USA
fYear
2009
fDate
7-9 Oct. 2009
Firstpage
164
Lastpage
172
Abstract
This paper presents fault modeling and analysis for open defects in a synchronizer that is implemented by two D flip-flops. Open defects are injected into any node of the synchronizer, and HSPICE is used to perform circuit analysis. The major purpose of this analysis is to find all possible faults that might occur in the synchronizer by open defects. The results obtained can be used to develop methods for testing the interfacing circuits between different clock domains which are implemented with the synchronizer.
Keywords
fault diagnosis; flip-flops; sequential circuits; synchronisation; D flip-flops; HSPICE; circuit analysis; fault modeling; resistive open defect; synchronizer; Circuit faults; Circuit testing; Clocks; Failure analysis; Flip-flops; Inverters; Metastasis; Predictive models; Synchronization; Timing; fault analysis; fault modeling; resistive open defect; synchronizer;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2009. DFT '09. 24th IEEE International Symposium on
Conference_Location
Chicago, IL
ISSN
1550-5774
Print_ISBN
978-0-7695-3839-6
Type
conf
DOI
10.1109/DFT.2009.34
Filename
5372261
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