Title :
Analysis of Resistive Open Defects in a Synchronizer
Author :
Kim, Hyoung-Kook ; Jone, Wen-Ben ; Wang, Laung-Terng
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Cincinnati, Cincinnati, OH, USA
Abstract :
This paper presents fault modeling and analysis for open defects in a synchronizer that is implemented by two D flip-flops. Open defects are injected into any node of the synchronizer, and HSPICE is used to perform circuit analysis. The major purpose of this analysis is to find all possible faults that might occur in the synchronizer by open defects. The results obtained can be used to develop methods for testing the interfacing circuits between different clock domains which are implemented with the synchronizer.
Keywords :
fault diagnosis; flip-flops; sequential circuits; synchronisation; D flip-flops; HSPICE; circuit analysis; fault modeling; resistive open defect; synchronizer; Circuit faults; Circuit testing; Clocks; Failure analysis; Flip-flops; Inverters; Metastasis; Predictive models; Synchronization; Timing; fault analysis; fault modeling; resistive open defect; synchronizer;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2009. DFT '09. 24th IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
978-0-7695-3839-6
DOI :
10.1109/DFT.2009.34
