• DocumentCode
    2956754
  • Title

    Reduced Precision Checking for a Floating Point Adder

  • Author

    Eibl, Patrick J. ; Cook, Andrew D. ; Sorin, Daniel J.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
  • fYear
    2009
  • fDate
    7-9 Oct. 2009
  • Firstpage
    145
  • Lastpage
    152
  • Abstract
    We present an error detection technique for a floating point adder which uses a checker adder of reduced precision to determine if the result is correct within some error bound. Our analysis establishes a relationship between the width of the checker adder´s mantissa and the worst-case magnitude of an undetected error in the primary adder´s result. This relationship allows for a tradeoff between error detection capability and area overhead that is not offered by any previously developed floating point adder checking schemes. Experimental results of fault injection experiments are presented which support our analysis.
  • Keywords
    adders; error detection; fault location; floating point arithmetic; area overhead; checker adder mantissa; error detection; fault injection; floating point adder; reduced precision checking; Fault tolerant systems; Very large scale integration; error detection; floating point adder;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 2009. DFT '09. 24th IEEE International Symposium on
  • Conference_Location
    Chicago, IL
  • ISSN
    1550-5774
  • Print_ISBN
    978-0-7695-3839-6
  • Type

    conf

  • DOI
    10.1109/DFT.2009.22
  • Filename
    5372263