Title :
A full-parallel architecture ASIC implementation of FP-based multilayered feedforward neural networks
Author :
Ling, Liu ; Yannan, Zhao ; Bo, Zhang
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
This paper describes an approach to the ASIC implementation of a multilayered feedforward neural network. Based on a new learning algorithm (Forward Propagation Algorithm), our system realizes a real full-parallel architecture and allows all of the neurons to work parallelly and independently. Hardware cost is greatly reduced and the network is easy to expand. The current results of our implementation using an Xinlinx FPGA chip are also presented
Keywords :
application specific integrated circuits; feedforward neural nets; field programmable gate arrays; learning (artificial intelligence); neural chips; neural net architecture; parallel architectures; ASIC implementation; FP-based neural networks; Xinlinx FPGA chip; forward propagation algorithm; full-parallel architecture; learning algorithm; multilayered feedforward neural networks; Application specific integrated circuits; Artificial neural networks; Computer architecture; Costs; Feedforward neural networks; Field programmable gate arrays; Multi-layer neural network; Neural network hardware; Neural networks; Neurons;
Conference_Titel :
ASIC, 1996., 2nd International Conference on
Conference_Location :
Shanghai
Print_ISBN :
7-5439-0940-5
DOI :
10.1109/ICASIC.1996.562820
