DocumentCode
2956844
Title
Design of 16-channel CAGO-CFAR ASIC block with target-eliminating circuit
Author
Xiao-yan, Wan ; Chuan-hui, Luo ; Chang-yao, Lhang ; Zhang-qi, Guo
Author_Institution
East China Res. Inst. of Electron. Eng., Hefei, China
fYear
1996
fDate
21-24 Oct 1996
Firstpage
340
Lastpage
343
Abstract
In this paper, a kind of circuit with the logarithm cell-averaging greatest-of selection (GO-CFAR) eliminating estimate cell target is introduced, which can make 16 channels CFAR processing in 4.8 μS. The main characteristics of the circuit which is single ASIC chip is designed with standard cells, and can eliminate the effect of big targets upon the estimate level. The chip consists of clock generator, arithmetic section and internal RAM with 11 K BIT, totally 13000 gates
Keywords
application specific integrated circuits; radar signal processing; target tracking; arithmetic section; clock generator; design; internal RAM; logarithm cell-averaging greatest-of selection eliminating estimate cell target; multichannel CAGO-CFAR ASIC chip; radar signal processing; standard cell; target-eliminating circuit; Application specific integrated circuits; Arithmetic; Clocks; Degradation; Delay estimation; Delay lines; Electronic switching systems; Equations; Filters; Wide area networks;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 1996., 2nd International Conference on
Conference_Location
Shanghai
Print_ISBN
7-5439-0940-5
Type
conf
DOI
10.1109/ICASIC.1996.562823
Filename
562823
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